The present invention relates to a mode switching method for a PLL circuit and a mode control circuit for a PLL circuit, and more particularly to a mode switching method for a PLL circuit and a mode control circuit for a PLL circuit having two modes, i.e., a high-speed mode and a normal mode.
In recent years, PLL circuits are used in PLL frequency synthesizers for mobile communications, e.g., cellular phone systems. There are a strict requirement for high-speed lock-up of PLL circuits and a strict requirement for high C/N ratios (carrier-to-noise ratios) and low-spurious leakage while PLL circuits are being locked. To meet these two contradicting requirements, a process for switching between a high-speed mode and a normal mode has been proposed. In the high-speed mode, the loop gain is high, and the PLL circuit is locked up at a high speed. In the normal mode, the loop gain is low, and a high C/N ratio and low spurious characteristics are obtained.
FIG. 1 of the accompanying drawings shows in block form a conventional PLL frequency synthesizer.
As shown in FIG. 1, a PLL circuit 80 has a phase comparator 84 which receives a reference frequency-divided signal LDR from a reference counter 82 and a comparison frequency-divided signal LDP from a main counter 83. The phase comparator 84 compares the phase of the reference frequency-divided signal LDR and the phase of the comparison frequency-divided signal LDP with each other, and generates an up pulse signal PU or a down pulse signal PD which has a pulse duration depending on the result of the comparison. A charge pump 85 receives the up pulse signal PU or the down pulse signal PD, and generates a current DO depending on the up pulse signal PU or the down pulse signal PD which has been received. The current DO is supplied through a low-pass filter (LPF) 86 to a VCO 87, whose oscillation frequency is controlled depending on the current DO.
When the reference frequency-divided signal LDR and the comparison frequency-divided signal LDP are in phase with each other, i.e., when the PLL circuit 80 is in a locked state, if the output current DO from the charge pump 85 is 0 (zero), then the system has a dead band. Therefore, the phase comparator 84 generates an up current and a down current. Since an output current flowing when the PLL circuit 80 is locked affects the C/N ratio and the spurious leakage, the output current is suppressed in the normal mode.
If the low-pass filter 86 of the PLL circuit 80 is fixed, then the lock-up time is shortened when the output current is large. Therefore, the output current DO of the charge pump 85 in the high-speed mode is set so as to be higher than in the normal mode, or to increase the pulse durations of the up pulse signal PU and the down pulse signal PD.
The normal mode and the high-speed mode are switched by a lock detecting circuit 89 which detects a locked state in accordance with the comparison output signal (the up pulse signal PU and the down pulse signal PD) from the phase comparator 84. The lock detecting circuit 89 generates a mode switching signal SW and supplies the mode switching signal SW to the charge pump 85. The lock detecting circuit 89 switches the normal mode and the high-speed mode in accordance with the locked state.
In the locked state, the frequency of the reference frequency-divided signal LDR and the frequency of the comparison frequency-divided signal LDP are the same as each other. When the phase difference between the signals LDR, LDP falls in a predetermined range, the lock detecting circuit 89 switches the high-speed mode to the normal mode.
The PLL circuit 80 with the low-pass filter 86 being fixed stably has the phase difference between the signals LDR, LDP due to the characteristics of the charge pump 85 and the low-pass filter 86. Therefore, the PLL circuit 80 is stable in different states in the high-speed mode and the normal mode. As a result, when the high-speed mode is switched to the normal mode, the PLL circuit 80 tends to be unlocked, increasing the phase difference between the reference frequency-divided signal LDR and the comparison frequency-divided signal LDP.
In such a case, the total lock-up time is the sum of the lock-up time in the high-speed mode and the re-lock-up time required to lock the PLL circuit from an unlocked state upon mode switching. In order to reduce the total lock-up time, therefore, it is necessary to reduce the re-lock-up time required due to the unlocked state.
However, after the lock detecting circuit 89 detects a locked state, the lock detecting circuit 89 generates a mode switching signal SW for changing from the high-speed mode to the normal mode. If the mode switching signal SW is supplied to the charge pump 85 while in operation, then the difference that is developed between the locked frequency and the unlocked frequency by the unlocking of the PLL circuit, i.e., the unlocked frequency interval, is widened.
If the unlocked interval is large, then the time required to reach a maximum unlocked frequency (maximum unlocked state reaching time) is increased when the PLL circuit is re-locked up, resulting in an increase in the re-lock-up time. As a result, the total lock-up time is increased.